San Jose State University
Student pursuing masters in Electrical Engineering and specializing in ASIC/VLSI/Digital Design and Verification. Graduating in May 2018.
LOOK BACK COMPRESSOR, SJSU, Oct-Nov 2017
• Group Project aiming to design a look back compressor to polish Verilog skills, use ASIC CMOS design's knowledge such as FIFO and Memory. Synthesize design...
FLOATING POINT ADDER MULTIPLIER USING FIFO, SJSU, September 2017
• Assignment to design FIFO and use it in given Floating Point Adder Multiplier using Verilog and Synthesize at 250 MHz.
64-Bit CONDITIONAL SUM and CARRY SELECT ADDERS
• Individual Project. Implemented, analyzed, simulated, synthesized and post-synthesized 64-bit Conditional Sum and Carry Select Adders in Verilog using EDA ...
TRANSMISSION GATE LOGIC BASED 32:1 MUX CIRCUIT USING CADENCE
• Individual Project. Created a 32:1 MUX circuit using Cadence in Cadence Virtuoso.
• Aimed to understand Cadence Virtuoso and apply CMOS circuit's knowledg...